build-fpga-xc7k480t
build-fpga-xc7k480t is a Build systems & CI pipelines skill for AI agents, published by mpskex in the chisel-npu repository on GitHub. Skillspace rates build-fpga-xc7k480t D (68/100) and it passed the safety scan; the rating is based on static analysis only.
Use when building the NPU FPGA bitstream for xc7k480tffg1156-2 — includes the squashed Vivado build flow (build_npu.tcl and build_npu_with_ila.tcl), bootstrap_project.tcl, the consolidated _apply_npu_topology.tcl BD library, ILA insertion, and bitstream configuration. Also use when modifying BD topology, RTL source (npu_ctrl_lite.v, npu_dma_master.v, npu_subsys.v), or Chisel top.sv regeneration.
- Grade
- D
- Quality
- 68 / 100
- Safety
- Passed
- GitHub stars
- 34
Unproven: rated by static analysis only, not yet compared head-to-head.
Our two independent classifiers differ on this skill's category, so treat the placement as provisional.
This rating describes the version of the repository we crawled; it may have changed since, so go by its current files.
Our review
- Architecture
- 100 / 100
- Maturity
- Basic: a single SKILL.md
- Security scan
- No issues found
- License
- GPL-2.0
- Adoption
- Adopted by 0 other repositories, in 0 collections
Not checked yet
- Not judged on the rubric yet (not a contender in its category)
- No blind task eval yet
- Scope (portable / vendor / repo-internal) not assessed; only the top of each category is read for scope
- Sibling files (scripts, references) not fetched; security scan covers SKILL.md only
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