erie-verilog-generator
erie-verilog-generator is an Embedded, IoT & robotics skill for AI agents, published by Eriemon in the verilog-generator repository on GitHub. Skillspace rates erie-verilog-generator C (72/100) and it passed the safety scan; the rating is based on static analysis only.
Use when Codex needs Chinese-language Verilog or RTL design, existing-RTL analysis, verify-repair planning, controlled improvement planning, semantic comparison, debugging, troubleshooting, independent static lint, self-checking testbench scaffolds, or ASIC-quality review for a Verilog-target design, including synthesizable Verilog-2001 RTL, local or remote Vivado/xsim validation, artifact extraction, and workflow trace diagnosis.
- Grade
- C
- Quality
- 72 / 100
- Safety
- Passed
- GitHub stars
- 201
Unproven: rated by static analysis only, not yet compared head-to-head.
This rating describes the version of the repository we crawled; it may have changed since, so go by its current files.
Our review
- Architecture
- 84 / 100
- Maturity
- Structured: ships references or scripts
- Security scan
- No issues found
- License
- Apache-2.0
- Adoption
- Adopted by 0 other repositories, in 0 collections
Not checked yet
- Not judged on the rubric yet (not a contender in its category)
- No blind task eval yet
- Scope (portable / vendor / repo-internal) not assessed; only the top of each category is read for scope
- Sibling files (scripts, references) not fetched; security scan covers SKILL.md only
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