logic-synthesis
logic-synthesis is an Embedded, IoT & robotics skill for AI agents, published by chuanseng-ng in the digital-chip-design-agents repository on GitHub. Skillspace rates logic-synthesis C (72/100) and it passed the safety scan; the rating is based on static analysis only.
Logic synthesis from RTL to gate-level netlist — SDC constraint validation, compile and optimisation strategy, netlist quality check, and LEC equivalence verification. Use when synthesising RTL for ASIC, setting up timing constraints, optimising for timing/area/power, or verifying a post-synthesis netlist.
- Grade
- C
- Quality
- 72 / 100
- Safety
- Passed
- GitHub stars
- 166
Unproven: rated by static analysis only, not yet compared head-to-head.
This rating describes the version of the repository we crawled; it may have changed since, so go by its current files.
Our review
- Architecture
- 84 / 100
- Maturity
- Packaged: licensed, with a version or references
- Security scan
- No issues found
- License
- MIT
- Adoption
- Adopted by 0 other repositories, in 0 collections
Not checked yet
- Not judged on the rubric yet (not a contender in its category)
- No blind task eval yet
- Scope (portable / vendor / repo-internal) not assessed; only the top of each category is read for scope
- Sibling files (scripts, references) not fetched; security scan covers SKILL.md only
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