reg-def-gen
reg-def-gen is an Embedded, IoT & robotics skill for AI agents, published by IC-Design-Verify in the wujian100_uvm repository on GitHub. Skillspace rates reg-def-gen B (81/100) and it passed the safety scan; the rating is based on static analysis only.
Generate uvm register-model companion headers (C .h for BSP and SystemVerilog .svh for testbench) from a Synopsys DesignWare IP databook text extract. Use when you need to produce project-convention RegDef.h/RegDef.svh files that match the layout used by `dv/simulation/verif_env/soc/header_files/` (one typedef-union per register, per-register offset + addr macros). The skill is IP-agnostic across Synopsys IP families (DW_apb_*, DW_axi_*, DWC_*) provided the input text uses the standard 'N.M.K REG_NAME' section markers and 'Table N-M Fields for Register: NAME' field tables.
- Grade
- B
- Quality
- 81 / 100
- Safety
- Passed
- GitHub stars
- 23
Unproven: rated by static analysis only, not yet compared head-to-head.
Our two independent classifiers differ on this skill's category, so treat the placement as provisional.
This rating describes the version of the repository we crawled; it may have changed since, so go by its current files.
Our review
- Architecture
- 100 / 100
- Maturity
- Structured: ships references or scripts
- Security scan
- No issues found
- License
- GPL-3.0
- Adoption
- Adopted by 0 other repositories, in 0 collections
Not checked yet
- Not judged on the rubric yet (not a contender in its category)
- No blind task eval yet
- Scope (portable / vendor / repo-internal) not assessed; only the top of each category is read for scope
- Sibling files (scripts, references) not fetched; security scan covers SKILL.md only
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