veriloga
veriloga is an Embedded, IoT & robotics skill for AI agents, published by Arcadia-1 in the veriloga-skills repository on GitHub. Skillspace rates veriloga D (65/100) and it passed the safety scan; the rating is based on static analysis only.
Write Verilog-A behavioral modules for analog/mixed-signal IC design (Cadence Virtuoso / Spectre). Covers 12 circuit categories. TRIGGER FIRST (before evas-sim) when the user needs to write or generate a new .va file. Key trigger phrases: "write", "create", "generate", "code", "implement" + "Verilog-A / veriloga / va / .va / behavioral model". Also triggers on: review/fix Verilog-A, "behavioral model", "veriloga", "analog HDL", circuit spec → behavioral model, "voltage-domain", "current-domain". Do NOT defer to evas-sim for authoring — evas-sim is for running an already-written file.
- Grade
- D
- Quality
- 65 / 100
- Safety
- Passed
- GitHub stars
- 26
Unproven: rated by static analysis only, not yet compared head-to-head.
This rating describes the version of the repository we crawled; it may have changed since, so go by its current files.
Our review
- Architecture
- 71 / 100
- Maturity
- Structured: ships references or scripts
- Security scan
- No issues found
- License
- Not declared. Check the repository before reusing it.
- Adoption
- Adopted by 0 other repositories, in 0 collections
Not checked yet
- Not judged on the rubric yet (not a contender in its category)
- No blind task eval yet
- Scope (portable / vendor / repo-internal) not assessed; only the top of each category is read for scope
- Sibling files (scripts, references) not fetched; security scan covers SKILL.md only
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