write-sim-testbench
write-sim-testbench is an Integration & environment testing skill for AI agents, published by xlsynth in the bedrock-rtl repository on GitHub. Skillspace rates write-sim-testbench C (71/100) and it passed the safety scan; the rating is based on static analysis only.
Write or update one Bedrock-RTL SystemVerilog simulation testbench and its Bazel sim target. Use when Codex needs to add, refactor, debug, or review a verilog_sim_test/br_verilog_sim_test_tools_suite bench for VCS or Verilator, including parameterized tests, ready/valid stimulus, scoreboards, and portable smoke/regression coverage that complements formal verification.
- Grade
- C
- Quality
- 71 / 100
- Safety
- Passed
- GitHub stars
- 43
Unproven: rated by static analysis only, not yet compared head-to-head.
Not launch-quality. It is graded C with a clean safety verdict, but our quality filters exclude it: it looks written only for the repository it lives in. So it is not in our launch-quality set, the skills our MCP server searches and recommends. How launch-quality is decided
This rating describes the version of the repository we crawled; it may have changed since, so go by its current files.
Our review
- Architecture
- 93 / 100
- Maturity
- Structured: ships references or scripts
- Security scan
- No issues found
- License
- Apache-2.0
- Adoption
- Adopted by 0 other repositories, in 0 collections
Not checked yet
- Category is a classifier prediction; no model has read this skill yet
- Not judged on the rubric yet (not a contender in its category)
- No blind task eval yet
- Scope (portable / vendor / repo-internal) not assessed; only the top of each category is read for scope
- Sibling files (scripts, references) not fetched; security scan covers SKILL.md only
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